The present invention relates to a circuit for modifying a clock pulse train, and more particularly but not exclusively to such a circuit in which a clock pulse train can be selectively supplied and, if supplied can be selectively inverted.
It is a known requirement to provide a gated clock pulse train which can be inverted or not according to user requirements. A known circuit receiving a clock pulse train and operable to either provide no clock, a true clock or an inverted clock has a disadvantage of different propagation times through the circuit depending on whether the clock is inverted or not. Known circuits also may present problems such as glitches when switching between inverting and non-inverting clocks.
It is accordingly an object of the present invention to at least partially mitigate the difficulties of the prior art.
According to the present invention there is provided a circuit for modifying a clock pulse train, the circuit comprising a input for said clock pulse train, a first logic circuit having an output which is responsive to a clock pulse edge of a first polarity, a second logic circuit having an output which is responsive to a clock pulse edge of a second polarity opposite to said first polarity and a two-input multiplexer having a control input coupled to receive said clock pulse train, the first input of the multiplexer receiving the output of the first logic and the second input of the multiplexer receiving the output of the second logic circuit.
Preferably the first logic circuit comprises a first latch circuit having an input and said second logic circuit comprises a second latch circuit having an input, the circuit further comprising a control input terminal connected to said input of said first latch and to said input of said second latch via respective paths, the propagation delay difference between said path being less than the period of a clock pulse.
According to a second aspect of the present invention there is provided a circuit for selectively modifying a clock pulse train, the circuit comprising an input for said clock pulse train, a first clocked latch having an input, an output and a clock terminal, a second clocked latch having an input, an output and a clock terminal, and a two input multiplexer having a control input connected to receive said clock pulse train, the first input of the multiplexer being connected to the output of the first latch and the second input of the multiplexer being connected to the output of the second latch, said input for said clock pulse train being connected to the clock input terminals of said first and second latches wherein the first latch is responsive to a rising edge in said clock pulse train and the second latch is responsive to a falling edge in said clock pulse train.
Preferably the circuit comprises a control input and an enable input, and first logic circuitry connecting said control input and said enable input to the input of said first latch and second logic circuitry connecting said control input and said enable input to the input of said second latch.
Conveniently said logic circuitry comprises a two input AND gate receiving said control input and enable input at its two inputs and said first logic circuitry comprises a two input AND gate receiving at its two inputs said enable input and the inverse of the said control input.
An embodiment of the present invention will be described by way of example only with reference to the accompanying drawings.